Field effect transistors (FET's) are routinely included in integrated circuitry with a metal-oxide-silicon (MOS) structure. The MOSFET design comprises a pair of diffusion regions, one referred to as a source and the other a drain, each spaced apart within a semiconductive material. This design includes a gate provided adjacent to a separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate separation region adjacent the gate and between the diffusion regions is referred to as a channel. The semiconductive substrate typically comprises silicon having a light conductivity dopant concentration.
To aid in interpretation of the claims that follow, the terms "semiconductive substrate" and "semiconductor substrate" are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A MOSFET structure is typically fabricated during semiconductor processing by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. There are generally two types of MOSFETs, namely an n-type transistor and a p-type transistor. These transistors are fabricated within the semiconductor substrate by using either n-type doped silicon that is rich in electrons or p-type doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of holes or electrons.
The semiconductor industry continually strives to decrease the device size of components in an integrated circuit thereby increasing the overall performance speed. Accordingly, p-type and n-type field effect transistors are routinely included in integrated circuitry fabrication adjacent one another in ever closer proximities. However, as the spacing between the n-type and p-type field effect transistors on a substrate decreased, undesired effects developed. A challenge in fabrication of both transistors is to synchronize the fabrication of the paired p-type and n-type devices so that desired performance is achieved. As a result, device design, and consequently process technology, had to be modified to take these effects into account so that optimum device performance could continue to be obtained.
The gates for each transistor type are routinely fabricated from the same polysilicon layer heavily doped with an n-type material. Such designs for p-type MOSFETs can include a p-type doped region formed within the channel region between the source/drain. However, as gate widths decrease to below 0.3 microns, this design can allow significant current leakage and increase the difficulty of designing MOSFETs with low threshold voltages to function with low power supplies. A solution is to heavily dope the p-transistor gates with p-type dopant instead of n-type dopant. However, this solution has its own problem. The p-type dopant can diffuse from the gate into the channel to cause significant current leakage between the source/drain regions.